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JAIT 2023 Vol.14(2): 355-362
doi: 10.12720/jait.14.2.355-362

Parallel Software Encryption of AES Algorithm by Using CAM-Based Massive-Parallel SIMD Matrix Core for Mobile Accelerator

Kyosuke Kageyama 1,*, Sota Arai 2, Hajime Hamano 2, Xiangbo Kong 2, Takeshi Kumaki 2, and Tetsushi Koide 3
1. Department of Electrical, Electronic and Communication Engineering, Kindai University, Osaka, Japan
2. Department of Electronic and Computer Engineering, Ritsumeikan University, Shiga, Japan; Email: {ri0077er @ed, ri0093fr@ed, kong@fc, kumaki@fc}.ritsumei.ac.jp (S.A., H.H., X.K., T.K.)
3. Research Institute for Nanodevices (RIND), Hiroshima University, Hiroshima, Japan; Email: koide@hiroshima-u.ac.jp (T.K.) *Correspondence: kageyama@ele.kindai.ac.jp (K.K.)

Manuscript received July 4, 2022; revised September 7, 2022; accepted October 13, 2022; published April 17, 2023.

Abstract—Recently, it has become possible to execute various digital multimedia applications, such as image compression, video compression, and audio processing, on mobile devices — as long as the processing core in the mobile device has the required high levels of performance, versatility, and programmability. Generally speaking, multimedia applications operate by performing repeated arithmetic and table-lookup coding operations. Therefore, to make it easier to achieve those required high levels of performance, versatility, and programmability, we propose an accelerator for mobile Central Processing Units (CPUs) known as a Content Addressable Memory-based massive-parallel Single Instruction Multiple Data (SIMD) Matrix Core (CAMX) that improves the processing speeds of both arithmetic and table-lookup coding operations. Our proposed CAMX, which is equipped with two CAM modules, has highly parallel processing capabilities that facilitate fast table-lookup coding operations. In fact, the results of Advanced Encryption Standard (AES) encryption simulations conducted in this study show that its AES encryption total clock cycles are 1,362,699. Additionally, a detailed breakdown of the number of clock cycles shows 1,312,160 for SubBytes, a combined total of 17,161 for ShiftRows and MixColumns, and 2519 for AddRoundKey. This paper also confirmed that CAMX could process AES encryptions at a rate of 83.17 clock cycles/byte. Also, the performance of CAMX, related works, and existing mobile processors are compared. The related works do not have a dedicated circuit for AES processing. From the comparison results, CAMX provides a performance improvement of approximately 4.4- and 3569.1-times over the related works. The existing mobile processors are Texas Instruments (TI) DM3730 and a TI OMAP3530. From the comparison results, CAMX provides a performance improvement of approximately 2.1 times over TI DM3730 and TI OMAP3530.
 
Keywords—CAMX, CAM, parallel processing, Single Instruction Multiple Data (SIMD), Advanced Encryption Standard (AES)

Cite: Kyosuke Kageyama*, Sota Arai, Hajime Hamano, Xiangbo Kong, Takeshi Kumaki, and Tetsushi Koide, "Parallel Software Encryption of AES Algorithm by Using CAM-Based Massive-Parallel SIMD Matrix Core for Mobile Accelerator," Journal of Advances in Information Technology, Vol. 14, No. 2, pp. 355-362, 2023.

Copyright © 2023 by the authors. This is an open access article distributed under the Creative Commons Attribution License (CC BY-NC-ND 4.0), which permits use, distribution and reproduction in any medium, provided that the article is properly cited, the use is non-commercial and no modifications or adaptations are made.